Adaptive Multi-Standard RF Front-Ends (Analog Circuits and by Vojkan Vidojkovic, J. van der Tang, Arjan Leeuwenburgh,

By Vojkan Vidojkovic, J. van der Tang, Arjan Leeuwenburgh, Arthur H.M. van Roermund

This ebook investigates recommendations, advantages, obstacles, and prices linked to multi-standard operation of RF front-ends and their skill to conform to variable radio environments. subsequent, it highlights the optimization of RF front-ends to permit greatest functionality inside a definite strength price range, whereas concentrating on complete integration. ultimately, the publication investigates percentages for low-voltage, low-power circuit topologies in CMOS know-how.

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SAW filters2 ). They are rather expensive [33]. com 38 CHAPTER 2. 20 Superheterodyne double-conversion front-end architecture possibility to implement tunability is very low. Therefore, flexibility of the IF sampling front-end architecture to accommodate requirements of different standards is low. Superheterodyne double-conversion front-end architecture The sampling frequency of the ADC, which can be relatively high in the superheterodyne front-end architecture, can be reduced applying the frequency down-conversion ones more.

In order to be converted into the digital domain by an ADC that has an acceptable power consumption (a few tens of mW), the frequency of an analog signal has to be sufficiently low. This means that an RF signal, which is received, has to be first downconverted to a lower Intermediate Frequency (IF). Obviously, the fourth front-end function is frequency down-conversion. This function is realized by a mixer. The mixer is a building block with three ports: RF input, Local Oscillator (LO) input and IF output.

In general, they should occupy less chip area and consume less power than an IFCF. A high level of integration and digitization are properties typical for the zero-IF architecture. A high level of digitization makes zero-IF architecture suitable for application in multi-standard front-end and for implementation in deep-submicron CMOS processes. The same as in the quadrature low-IF architecture, the flexibility with respect to different standards is influenced by the frequency range in which QLO provide I/Q signals.

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